This invention relates to digital computer emulators; and more particularly, it relates to the architecture and operating speed of such emulators.
Currently, there are many different manufacturers of digital computers; and, each manufacturer makes its computers such that they execute their own uniquely formatted set of instructions. For example, a Motorola 68030 microprocessor is designed to execute a 68030 set of instructions, whereas an Intel 80.times.86 microprocessor is designed to execute an 80.times.86 set of instructions ("X" is 2 or 3). Since each such set of instructions has its own unique format, user programs which are written with 80.times.86 instructions cannot run directly on the Motorola 68030 microprocessor; and vice versa.
On the other hand, user programs which are written for the computer of one manufacturer (the target computer) often perform functions which the users of computers of other manufacturers (the host computer) would also like to perform. But to rewrite a long and complicated program from one computer's instruction set to another computer's instruction set can be very time-consuming and expensive. Consequently, computer emulators have been developed.
In one common form, an emulator consists entirely of a software program called an emulator program which consists entirely of host computer instructions. This emulator program sequentially examines all the fields of the target machine instruction that is being emulated, forms the addresses of the operands which those fields specify, retrieves the operands, performs an operation on those operands, and stores the result.
However, to perform all of the above tasks for just one instruction of the target machine takes many host instructions in the emulator program. For example, to perform a single target machine instruction can easily take fifty to one hundred fifty instructions in the emulator program. Thus, the execution time of such an emulator is inherently slow.
Accordingly, a primary object of the invention is to provide a novel and economical architecture for an emulator in which emulation speed is substantially increased.